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In this paper, the authors present a hardware efficient architecture for vector rotations based on the CORDIC (COordinate Rotation DIgital Computer) algorithm. In its original form the CORDIC suffers from major drawbacks like scale-factor calculation, latency and optimal selection of microrotations. The proposed algorithm overcomes all these drawbacks. They use leading-one bit detection technique to identify the micro-rotations. The scale-free design of the proposed algorithm is based on Taylor series expansion of the sine and cosine functions. The 16-bit pipelined architecture requires 29.86% less logic gates, consumes on an average 36.84% less power, and has 37.3% less delay when compared to Xilinx CORDIC-IP v 3.0.