Area Reduction of Test Pattern Generation Used in BIST Schemes

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Provided by: International Journal of Engineering Trends and Technology
Topic: Hardware
Format: PDF
In this paper, the author proposes a Test Pattern Generator (TPG) for built-in self-test. This method generates Multiple Single Input Change (MSIC) vector, which in turn are applied to the scan chain. The existing methodology uses Johnson counter, XOR gate and LFSR for generating multiple single input change vector. But, the drawback of the previous technique was more area consumption. Hence, in order to reduce the area, multiple single input change vectors are generated using Johnson counter and accumulator.
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