Association for Computing Machinery
Decreasing the traffic from CPU LLC to main memory is a very important issue in modern systems. Recent paper focuses on cache misses, overlooking the impact of writebacks on the total memory traffic, energy consumption, IPC, etc. Policies which foster a balanced approach, between reducing write traffic to memory and improving miss-rates can increase overall performance, improve energy efficiency and memory system lifetime for NVM memory technology, such as Phase-Change Memory (PCM). The authors propose Adaptive Replacement and Insertion (ARI), an adaptive approach to last level CPU cache management, optimizing the two parameters (miss rate and writeback rate) simultaneously.