ASCIB: Adaptive Selection of Cache Indexing Bits for Removing Conflict Misses

Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
With the scaling of transistors following Moore's law, the significance of the memory hierarchy to the overall system performance continues growing. The design of the first level cache is an important parameter for achieving high performance systems since it is accessed in the critical path of the processor, which determines the clock frequency of the system. The design of cache memories is a crucial part of the design cycle of a modern processor. Unfortunately, caches with low degrees of associatively suffer a large amount of conflict misses, while high-associative caches consume more power per access.

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