Institute of Electrical & Electronic Engineers
A unified algorithm-architecture-circuit co-design environment for dedicated signal processing hardware is presented. The approach is based on a single design description in the graphical Matlab/Simulink environment that is used for FPGA emulation, ASIC design, verification and chip testing. This unified description enables system designer with a visibility through several layers of design hierarchy down to circuit level to select the optimal architecture. The tool flow propagates up circuit-level performance and power estimates to rapidly evaluate architecture-level tradeoffs.