Designing multiplier is always a challenging and interesting job, in order to satisfy user needs as per demand. Vedic multiplier is prominent system for faster result and optimized circuit design. In any digital system the throughput and power consumption decides the performance. The paper concentrated on Vedic multiplier power consumption and throughput. In much faster computing and parallel processing architectures, pipeline motivates for higher throughput. This is motivated to incorporate pipeline in the present paper to enhance the performance of the Vedic multiplier.