ASIC Implementation of a High Speed, Low Area Reconfigurable Decimation Filter
Decimation filter is used to reduce the sampling rate for succeeding stages of an oversampling ADC. The speed of a successive-approximation ADC predominately depends on the decimator speed. This necessitates a need to design a high speed decimation filter to improve the overall system performance. A reconfigurable architecture is applied for the design of decimator to serve this purpose. Results show that delay of a reconfigurable decimator is reduced by 29.74% compared to a normal decimation filter.