ASIC Implementation of High Speed Processor for Calculating Discrete Fourier Transformation using Circular Convolution Technique

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Provided by: WSEAS
Topic: Hardware
Format: PDF
The improvement in speed and power for calculating discrete Fourier transformation using circular convolution is well established, but all the work so far been reported are at FPGA (gate) level. In this paper, ASIC implementation of high speed processor for calculating Discrete Fourier Transformation (DFT) based on circular convolution architectures is reported for the first time. The IEEE-754 single precision format was considered for the representation of the twiddle factors. The improvement of the speed for floating point multiplication/addition was achieved by canonical sign digit implementation methodology, which reduced the stages of operation significantly.
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