ASIC Implementation of Multi-Threaded Pipelined Aes Crypto Processor
In this paper, the authors present AES algorithm implementation using multi-threaded and pipelining concept for faster data encryption and its physical implementation using 40nm technology. AES crypto-algorithm is widely used in secured wireless communications, zigbee, Electronic financial transactions, content protection, digital rights, set-top boxes etc. The AES algorithm is symmetric block cipher 128/192/256 bit key which takes 10/12/14 rounds for encryption respectively. The design provides highest throughput of 6.22 Gbps and dynamic power dissipation of 1.3209 mw.