ASIC Implementation of STM-1 Framer and De-Framer
In this paper, the authors present the ASIC implementation of STM-1 framer and de-framer. This paper mainly focuses on multiplexing digital data, transmitting and receiving the STM-1 frame. The design is implemented using Verilog HDL, simulated on Modelsim and synthesized on Xilinx ISE 13.2. For power analysis and area calculation, the designed framer and de-framer are analyzed using Cadence version 6.1.5. For debugging chipscope analyzer has been used. The designed framer can be used for generation and analysis of STM-1 frame that has a data rate of 155.52Mbps.