ASIC Implementation of Switchable Key AES Cryptoprocessor
In this paper the authors present the ASIC implementation of switchable key advanced encryption standard algorithm encryption and decryption with power gating. The implementation supports 128 bits, 192 bits and 256 bits key. The design is described using verilog HDL, simulated in VCS synopsys. The RTL is synthesized in Design Compiler (DC) using Nangate 45nm open cell library and physical design is performed in ICC of synopsys. The design was clocked at 125M with a throughput of 1.14Gbps and the power consumption of 1.07mw.