ASIC Implementations of the Block Cipher SEA for Constrained Applications
SEA is a scalable encryption algorithm targeted for small embedded applications. It was initially designed for software implementations in controllers, smart cards or processors. In this paper, the authors investigate its hardware performances in a 0.13 m CMOS technology. For these purposes, different designs are detailed. A single clock cycle per round loop architecture is implemented. Beyond its low cost performances, a significant advantage of the proposed encryption core is its full flexibility for any parameter of the scalable encryption algorithm, taking advantage of generic VHDL coding.