ASIP-Based Multiprocessor SoC Design for Simple and Double Binary Turbo Decoding

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Provided by: European Design and Automation Association
Topic: Hardware
Format: PDF
In this paper, the authors present a new multiprocessor platform for high throughput turbo decoding. The proposed platform is based on a new configurable ASIP combined with an efficient memory and communication interconnect scheme. This Application-Specific Instruction-set Processor (ASIP) has SIMD architecture with a specialized and extensible instruction-set and 5-stages pipeline control. The attached memories and communication interfaces enable the design of efficient multiprocessor architectures. These multiprocessor architectures benefit from the recent shuffling technique introduced in the turbo-decoding field to reduce communication latency.
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