Assessing Fat-Tree Topologies for Regular Network-on-Chip Design under Nanoscale Technology Constraints

Provided by: edaa
Topic: Hardware
Format: PDF
Most of past evaluations of fat-trees for on-chip interconnection networks rely on over simplifying or even unrealistic architecture and traffic pattern assumptions, and very few layout analyses are available to relieve practical feasibility concerns in nano-scale technologies. This paper aims at providing an in-depth assessment of physical synthesis efficiency of fat-trees and at extrapolating silicon aware performance figures to back-annotate in the system-level performance analysis. A 2D mesh is used as reference architecture for comparison, and a 65 nm technology is targeted by the authors' study.

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