Provided by: International Journal of Computer Theory and Engineering (IJCTE)
Date Added: Jan 2014
In this paper, the authors present a low power asynchronous 10-bit Successive Approximation Register (SAR) ADC implemented in 0.18 CMOS process. The ADC is realized fully differentially with a split capacitor array to lower power cost and improve the speed. To further enhance power efficiency and high speed for a relatively moderate resolution, a new asynchronous dynamic logic is utilized to lower the digital power. The multiple-phase clock is generated by a ring-oscillator structure which avoids the high external clock. Offset of the dynamic clocked-comparator is also calibrated through adjusting the threshold voltage.