AUDIT: Stress Testing the Automatic Way

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Provided by: University of Teramo
Topic: Hardware
Format: PDF
Sudden variations in current (large di/dt) can lead to significant power supply voltage droops and timing errors in modern microprocessors. Several papers discuss the complexity involved with developing test programs, also known as stressmarks, to stress the system. Authors of these papers produced tools and methodologies to generate stressmarks automatically using techniques such as integer linear programming or genetic algorithms. However, nearly all of the previous work took place in the context of single-core systems, and results were collected and analyzed using cycle-level simulators. In this paper, the authors measure and analyze di/dt issues on state-of-the-art multi-core x86 systems using real hardware rather than simulators.
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