Automated Construction of a Cycle-Approximate Transaction Level Model of a Memory Controller

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Provided by: European Design and Automation Association
Topic: Hardware
Format: PDF
Modern System-on-Chip (SoC) designs are very complex and, thus, very hard to simulate and verify. The conventional Register Transfer Level (RTL) modeling is of too fine granularity to allow whole system designs to be rapidly simulated or used as virtual prototypes. Therefore, another more abstract level of modeling, namely Electronic System Level (ESL) has to be applied. ESL concentrates on abstract models of hardware components, which manage to keep the same or approximately the same timing accuracy as an RTL one, but execute much faster than their RTL counterparts.
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