Institute of Electrical & Electronic Engineers
Three-Dimensional Stacked Integrated Circuits (3D-SICs) implemented with Through-Silicon Vias (TSVs) and micro-bumps open new horizons for faster, smaller, and more energy-efficient chips. As all micro-electronic structures, these 3D chips and they interconnects need to be tested for manufacturing defects. Previously, the authors defined, implemented, and automated a 3D-DfT (Design-for-Test) architecture that provides modular test access for 3D-SICs containing monolithic logic dies in a single-tower stack. However, the logic dies comprising a 3D-SIC typically are complex System-on-Chip (SoC) designs that include embedded Intellectual Property (IP) cores, wrapped for modular test.