Automated Mapping of the MapReduce Pattern onto Parallel Computing Platforms

Provided by: Springer Healthcare
Topic: Hardware
Format: PDF
The MapReduce pattern can be found in many important applications, and can be exploited to significantly improve system parallelism. Unlike previous paper, in which designers explicitly specify how to exploit the pattern, the authors develop a compilation approach for mapping applications with the MapReduce pattern automatically onto Field-Programmable Gate Array (FPGA) based parallel computing platforms. They formulate the problem of mapping the MapReduce pattern to hardware as a geometric programming model; this model exploits loop-level parallelism and pipelining to give an optimal implementation on given hardware resources.

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