University of Pécs
The annual increase of chip complexity is 58%, while human designer's productivity increase is limited to 21%1. A drastic increase in designer productivity is only possible through the adoption of methodologies and tools that raise the design abstraction level, ingeniously hiding low-level, time-consuming, error-prone details. EDA methodologies as High-Level Synthesis (HLS) aim to generate synthesizable and verifiable RTL (Register Transfer Level) designs from algorithmic descriptions. An overview of FSMD modeling can be found in, where synchronous communication among modules is not discussed.