Colorado State University
As System-on-Chip (SoC) designs become more complex, it becomes increasingly harder to design communication architectures which satisfy design constraints. Manually traversing the vast communication design space for constraint driven synthesis is not feasible anymore. In this paper, the authors propose an approach that automates the synthesis of bus-based communication architectures for systems characterized by (possibly several) throughput constraints. Their approach accurately and effectively prunes the large communication design space to synthesize a feasible low-cost bus architecture which satisfies the constraints in a design.