Provided by: University of Washington
Date Added: Jul 2006
In this paper, the authors present tools that automate the creation of domain-specific CPLDs, targeted for SoC. By tailoring full-crossbar based CPLDs to the domains that they support, they provide results that beat fixed reconfigurable architectures by 5.5x to 11.8x on average in terms of area-delay product. They also create sparse-crossbar based CPLD architectures, using a novel switch smoothing algorithm that makes the crossbars amenable to layout. This algorithm reduced the wire jog pitch of their largest layout from 48 to just 3, allowing for a compact VLSI layout.