To specify, design, and implement complex System-on-Chip (SoC), a new modeling method, Transaction Level Modeling (TLM), has been proposed recently. TLM allows designers to focus on functionality while abstracting implementation details. At the Register Transfer Level (RTL), however, different modules communicate through detailed pin level signaling. SoC design methodologies involve the integration of different Intellectual Property (IP) blocks modeled at different levels of abstraction. Therefore a special module or channel is needed in order to link modules, IPs, designed at different abstraction levels.