Automatic Insertion of Low Power Annotations in RTL for Pipelined Microprocessors

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Provided by: edaa
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The authors propose a new technique for low power microprocessor design, a fine-grained clock gating scheme implemented at the RTL or the architectural level which utilizes the program structure of the model. Their algorithm automatically identifies fine-grained blocks of circuit which are not used on any given cycle during the execution of a particular instruction, and shuts them down. This scheme of slicing the circuit based on the instruction being executed is termed instruction-driven slicing. All prior approaches towards analyzing and optimizing RTL and architectural models for lower power dissipation suffer from modeling the power dissipation for very specific hardware structures.
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