Automatic Mapping of Nested Non-Counting Loop onto FPGAs

Provided by: AICIT
Topic: Hardware
Format: PDF
At present, most C2VHDL compiler uses FSM (Finite State Automaton) design method, it is easy to compile counting loop because the loop of initial value, final value and the step value known in compile. Because nested non-counting loop's index could not been known before program execution, FSM design method is complex to achieve, most C2VHDL compiler tools do not support nested non-counting loop. This paper, based on ASCRA compiler framework which is based on LLVM (Low Level Virtual Machine), presents a compilation algorithm which adapts one cycle of high level signal instead of FSM method to support multiple format nested non-counting loop.

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