Provided by: AICIT
Date Added: Sep 2013
The authors present an asynchronous SRAM system dividing multiple regions to improve the performance in this paper. As growing the number of memory regions, the hardware complexity is increase and the performance is enhanced. Thus, there is a trade-off between the performance and the hardware complexity. They analyze the relationship between both of them. Then, they determine the number of memory regions according to the memory size. From the simulation result, the proposed asynchronous SRAM shows 2.1 times higher performance compared to the conventional unified SRAM.