Provided by: International Journal of Recent Technology and Engineering (IJRTE)
The AXI acquiescent DDR3 controller allows access of DDR3 memory via AXI bus interface. The DDR3 controller labors as an essential bridge between the AXI host and DDR3 memory. This paper describes the implementation of AXI acquiescent DDR3 memory controller. It discusses the overall architecture of the DDR3 controller; it also discusses the AXI protocol operation. The DDR3 memory controller compares with DDR1 and DDR2 in performance wise. The design is simulated and synthesized on Xilinx ISE 13.2 successfully.