Balancing On-Chip Network Latency in Multi-Application Mapping for Chip-Multiprocessors

Provided by: University of Southampton
Topic: Hardware
Format: PDF
As the number of cores continues to grow in Chip Multi-Processors (CMPs), application-to-core mapping algorithms that leverage the non-uniform on-chip resource access time have been receiving increasing attention. However, existing mapping methods for reducing overall packet latency can-not meet the requirement of balanced on-chip latency when multiple applications are present. In this paper, the authors address the looming issue of balancing minimized on-chip packet latency with performance-awareness in the multi-application mapping of CMPs. Specifically, the proposed mapping problem is formulated, its NP-completeness is proven, and an efficient heuristic-based algorithm for solving the problem is presented.

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