Behavioral Model of Split Capacitor Array DAC for Use in SAR ADC Design

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Provided by: IRD India
Topic: Hardware
Format: PDF
A model of a switched capacitor Digital-to-Analog Converter (DAC) based on a split capacitor array is presented for use during the design of a Successive Approximation Register (SAR) ADC. The model takes the effects of parasitic capacitors into account, and the values of these parasitic capacitors can be extracted from the circuit topology by using caliber by mentor graphics or a similar tool. The influence of the two main parasitic capacitor types (those parallel to and those common to the capacitors in the arrays) on the DAC characteristics is analyzed.
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