Association for Computing Machinery
The latest advancements in the commercial formal model checkers have enabled the integration of formal property verification with the conventional testbench based methods in the overall verification plan. This has led to significant verification productivity across the entire design flow (from architectural verification to post-silicon debugging). As verification productivity is improved, debugging efficiency has become more important than before. In this paper, the authors discuss how formal technology can be leveraged to bring efficiency in the debugging process.