Provided by: IDOSI
Date Added: Sep 2014
A novel low-power and high speed 1-bit full-adder is described which is designed based on pass transistor and Transmission Gate (TG) logic. The main advantage of this design is its inherent very low propagation delay and low power consumption. The consequence of which leads to achieving lower Power Delay Product (PDP) than others designs. Intensive HSPICE simulation shows that the new full-adder consumes around 40% less power than the SS16T adder; moreover its Energy Delay Product (EDP) is 49.4% less than the SS16T full-adder.