Carnegie Mellon University
In Commercial-Off-The-Shelf (COTS) multi-core systems, a task running on one core can be delayed by other tasks running simultaneously on other cores due to interference in the shared DRAM main memory. Such memory interference delay can be large and highly variable, thereby posing a significant challenge for the design of predictable real-time systems. In this paper, the authors present techniques to provide a tight upper bound on the worst-case memory interference in a COTS-based multi-core system. They explicitly model the major resources in the DRAM system, including banks, buses and the memory controller. By considering their timing characteristics, they analyze the worst-case memory interference delay imposed on a task by other tasks running in parallel.