Institute of Electrical & Electronic Engineers
A microprocessor's performance is fundamentally limited by the rate at which it can resolve branch mispredictions. Control Independence (CI) architectures look for useful control and data independent instructions to fetch and execute in the shadow of a branch misprediction. This paper demonstrates that CI architectures can be guided to exploit substantial Branch-mispredict Level Parallelism (BLP) in existing control intensive applications. A program has Branch-mispredict Level Parallelism (BLP) when its dynamic execution trace contains hard-to-predict branches that are both control and data independent, and thus could, potentially, be resolved in parallel.