Buffer Depth Allocation for Thermal-Aware 3D Network-on-Chip Design

In this paper, the authors proposed a buffer allocation algorithm to configure 3D NoC for the traffic and power migration of the thermal-aware designs. While the direct simulation is time-consuming, the proposed queuing model for 3D NoC router enables rapid detection of the performance-bottleneck layer, which buffers allocated to. With the same buffer budget, the non-uniform buffer set from proposed algorithm improve throughputs than the uniform buffer set by 15.3% and 6.8%, under the uniform and transpose traffic respectively. And the non-uniform buffer set also reduces the peak temperature of 3D NoC.

Provided by: National Taiwan University Topic: Hardware Date Added: May 2010 Format: PDF

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