Buffer-Integrated-Cache: A Cost-Effective SRAM Architecture for Handheld and Embedded Platforms

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Provided by: Association for Computing Machinery
Topic: Storage
Format: PDF
In a SoC, building local storage in each accelerator is area inefficient due to the low average utilization. In this paper, the authors present design and implementation of Buffer-integrated-Caching (BiC), which allows many buffers to be instantiated simultaneously in caches. BiC enables cores to view portions of the SRAM as cache while accelerators access other portions of the SRAM as private buffers. They demonstrate the cost-effectiveness of BiC based on recognition MPSoC that includes two Pentium cores, an augmented reality accelerator and a speech recognition accelerator.
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