Buffer Minimization in RTL Synthesis From Coarse-Grained Dataflow Specification

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Provided by: Seoul metropolitan government
Topic: Hardware
Format: PDF
System level design methodology gains considerable research attention as the design complexity and the time-to-market pressure increase for System-on-Chip (SoC) design. In system level design, a system level specification is mapped to an optimal architecture in a systematic way and the mapping is evaluated before implementation for fast design space exploration. As a specification model in this paper, the authors are concerned with a coarse-grain dataflow model that is adopted in many high level design frameworks, especially for signal processing and multimedia applications because of formality and readability.
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