BuildMaster: Efficient ASIP Architecture Exploration Through Compilation and Simulation Result Caching

Provided by: Eindhoven University of Technology
Topic: Hardware
Format: PDF
In this paper, the authors introduce and discuss the build-master framework. This framework supports the design space exploration of application specific VLIW processors and offers automated caching of intermediate compilation and simulation results. Both the compilation and the simulation cache can greatly help to shorten the exploration time and make it possible to use more realistic data for the evaluation of selected designs. In each of the experiments they performed, they were able to reduce the number of required simulations with over 90% and save up to 50% on the required compilation time.

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