Institute for Innovation in Science & Technology (IIST)
In this paper, an accumulator-based 3-weight test pattern generation scheme is presented. The proposed scheme copes with the inherent drawbacks of the scheme proposed more precisely. First, it does not impose any requirements about the design of the adder i.e., it can be implemented using any adder design and then it does not require any modification of the adder; and hence it does not affect the operating speed of the adder. Furthermore, the proposed scheme compares favourably to the scheme proposed in terms of the required hardware overhead.