Butterfly and Benes-Based on-Chip Communication Networks for Multiprocessor Turbo Decoding

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Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
Several research activities have recently emerged aiming to propose multiprocessor implementations in order to achieve flexible and high throughput parallel iterative decoding. Besides application algorithm optimizations and application-specific instruction-set processor design, the on-chip communication network constitutes a major issue in this application domain. In this paper, the authors propose to use multistage interconnection networks as on-chip communication networks for parallel turbo decoding. Adapted Benes and Butterfly networks are proposed with detailed hardware implementation of network interfaces, routers, and topologies.
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