Cache Aware Compression for Processor Debug Support

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Provided by: edaa
Topic: Hardware
Format: PDF
During post-silicon processor debugging, the authors need to frequently capture and dump out the internal state of the processor. Since internal state constitutes all memory elements, the bulk of which is composed of cache, the problem is essentially that of transferring cache contents off-chip, to a logic analyzer. In order to reduce the transfer time and save expensive logic analyzer memory, they propose to compress the cache contents on their way out. They present a hardware compression engine for cache data using a cache aware compression strategy that exploits knowledge of the cache fields and their behavior to achieve an effective compression.
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