Cache-Oblivious VAT-Algorithms

Provided by: Cornell University
Topic: Hardware
Format: PDF
Modern processors have a memory hierarchy and use virtual memory. The authors concentrate on two-levels of the hierarchy and refer to the faster memory as the cache. Data is moved between the fast and the slow memory in blocks of contiguous memory cells, and only data residing in the fast memory can be accessed directly. Whenever data in the slow memory is accessed, a cache fault occurs and the block containing the data must be moved to the fast memory. In the EM-model of computation, the complexity of an algorithm is defined as the number of cache faults.

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