Cache Sharing Management for Performance Fairness in Chip Multiprocessors

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Provided by: Tsihai
Topic: Hardware
Format: PDF
Resource sharing can cause unfair and unpredictable performance of concurrently executing applications in Chip Multi-Processors (CMP). The shared last-level cache is one of the most important shared resources because off-chip request latency may take a significant part of total execution cycles for data intensive applications. Instead of enforcing ideal performance fairness directly, prior work addressing fairness issue of cache sharing mainly focuses on the fairness metrics of cache miss numbers or miss rates. However, because of the variation of cache miss penalty, fairness on cache miss cannot guarantee ideal fairness.
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