CACTI-3DD: Architecture-Level Modeling for 3D Die-Stacked DRAM Main Memory

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Provided by: European Design and Automation Association
Topic: Storage
Format: PDF
Modern computer systems demand ever-increasing performance, power-efficiency, and capacity from Dynamic Random Access Memories (DRAMs) to meet system performance requirements. Emerging 3D die-stacked DRAM technology is one of the most promising solutions for future memory architectures to satisfy the ever-increasing demands on performance, power, and cost. This paper introduces CACTI-3DD, the first architecture-level integrated power, area, and timing modeling framework for 3D die-stacked off-chip DRAM main memory. CACTI-3DD includes TSV models, improves models for 2D off-chip DRAM main memory over current versions of CACTI, and includes 3D integration models that enable the analysis of a full spectrum of 3D DRAM designs from coarse-grained rank-level 3D stacking to bank-level 3D stacking.
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