Colorado State University
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern Multi-Processor System-on-Chips (MPSoCs). However, customization of such architectures for an application requires the exploration of a large design space. Thus designers need tools to rapidly explore and evaluate relevant communication architecture configurations exhibiting diverse power and performance characteristics. In this paper, the authors present an automated framework for fast system-level, application-specific and power-performance trade-offs in bus matrix communication architecture synthesis.