Institute of Electrical & Electronic Engineers
On-chip communication architectures have a significant impact on the power consumption and performance of emerging Chip Multi-Processor (CMP) applications. However, customization of such architectures for an application requires the exploration of a large design space. Designers need tools to rapidly explore and evaluate relevant communication architecture configurations exhibiting diverse power and performance characteristics. In this paper, the authors present an automated framework for fast system-level, application-specific, power - performance tradeoffs in a bus matrix communication architecture synthesis.