Characterizing the Costs and Benefits of Hardware Parallelism in Accelerator Cores

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Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
Power and utilization constraints are limiting the performance gains of traditional architectures. Designers are increasingly embracing specialization to improve performance in the era of dark-silicon. General purpose processors are beginning to resemble SoC's from the embedded domain, and now include many specialized accelerator cores to improve computation throughput while reducing the energy-cost of computation. The design-space of accelerator cores is wide and varied. Designers are able to specify how much parallelism to expose in hardware by varying input width, pipeline depth, number of compute-lanes, etc.
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