Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline

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Provided by: University of Illinois at Urbana Champaign
Topic: Hardware
Format: PDF
The progression of implementation technologies into the sub-100 nanometer lithographies renew the importance of understanding and protecting against single-event upsets in digital systems. In this work, the effects of transient faults on high performance microprocessors are explored. To perform a thorough exploration, a highly detailed register transfer level model of a deeply pipelined, out-of-order microprocessor was created. Using fault injection, the authors determined that fewer than 15% of single bit corruptions in processor state result in software visible errors.
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