Charge Redistribution Based 8 Bit SAR ADC
An 8-bit 10 MS/s SAR A/D converter is presented. In the circuit design, a capacitor switched D/A converter architecture, dynamic latched comparator architecture and low power SAR logic are utilized. Design challenges and considerations are also discussed. This proposed converter is implemented based on 0.29um CMOS logic process. With a 3.3 V analog supply and a 5 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively.