Institute of Electrical and Electronics Engineers
In this paper, the authors propose a fast and accurate chip/package thermomechanical stress co-analysis tool for Through-Silicon-Via (TSV)-based 3-D ICs. They use their tool for full stack mechanical reliability as well as stress-aware timing analyses. First, they analyze the stress induced by chip/package interconnect elements, i.e., TSV and package bump. Second, they explore and validate the principle of Lateral and Vertical Linear Superposition (LVLS) of stress tensors considering all chip/package elements. The proposed LVLS method greatly reduces the complexity of stress calculation compared with the conventional finite element analysis method with high enough accuracy for full chip/package-scale stress simulations and reliability analysis.