Classification and Elimination of Conflicts in Hardware Transactional Memory Systems

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Provided by: INRIA
Topic: Storage
Format: PDF
In this paper, the authors analyze the sources of performance losses in hardware transactional memory and investigate techniques to reduce the losses. It dissects the root causes of data conflicts in Hardware Transactional Memory systems (HTM) into four classes of conflicts: true sharing, false sharing, silent store, and write-write conflicts. These conflicts can cause performance and energy losses due to aborts and extra communication. To quantify losses, the paper first proposes the 5C cache-miss classification model that extends the well-established 4C model with a new class of cache misses known as contamination misses.
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